IMEC passive photonic cSOI 220nm
This is IMEC's key process for passive photonic functions in a crystalline SOI film of 220nm thickness.
Key aspects
- 200mm silicon-on-insulator, 220nm top Si film, 2000nm burried oxide (BOX)
- 193nm deep UV lithography
- Typical/minimum line width [nm]: 450 / 120
- Typical/minimum pitch [nm]: 400 / 300
- Photonic wire losses 2.5-3dB/cm
- Best effort
Design kit
After signing the NDA with IMEC, we will provide you with a design kit containing a technology description, design rules, design guidelines and settings files for some mask design software. Just send us an e-mail.
Die size
The IMEC process works with a standard die size of 12.5mmx8.6mm.
- Each die is divided into 6 blocks of 6.1mmx2.5mm which can be allocated by the any user. The rest of the die is reserved for process control, alignment markers, etc.
- Each user can allocate one or more adjacent blocks as described on the block allocation file.
- The die is by default replicated over the wafer with a 14mmx10mm step, allthough a more dense map is available as well.
- Several wafer dicing options are available
Process modules
The process consists of a number of process modules:
| module | optional | included by default | number of masklevels |
|---|---|---|---|
| (wafer labeling - common for all wafers) | no | yes | - |
| clean | no | yes | - |
| 70nm silicon etch | yes | yes | 1 |
| 160nm silicon etch | yes | no | 1 |
| 220nm silicon etch | yes | yes | 1 |
| top oxide (not planarizing) | yes | no | - |
| substrate thinning | yes | no | - |
| dicing | yes | yes | - |
Currently, the user can choose to leave out some modules as indicated. Do not forget to mention this when signing in to a run. Keep in mind that each masked module requires a masklevel (and associated mask cost) !
Predefined masks
IMEC offers a number of predefined masks which can be re-used without additional mask cost.